The present disclosure relates to semiconductor devices and, more particularly, to variable resistance memory devices. A variable resistance memory device may include a resistance sensing element (e.g., a variable resistance layer) and may use a current transmission characteristic of the resistance sensing element in accordance with an applied voltage. In the variable resistance memory device, conductive/interconnect lines (e.g., bit lines or source lines) may be electrically connected to an upper portion and a lower portion of a variable resistance layer. Therefore, in the variable resistance memory device, line resistance or parasitic resistance of the conductive/interconnect lines may be undesirably high and a circuit configuration may be undesirably complex.